HDI PCBs are no longer reserved for exotic aerospace or telecom hardware. Today they appear in medical devices, automotive ADAS modules, wearable electronics, and compact industrial controllers. Routing these boards demands a different mindset from standard rigid PCB design. The limited space between fine-pitch BGAs, the need for laser-drilled microvias, and the tight impedance targets all force layout engineers to plan every trace, via, and plane transition before routing begins. The following sections explain how to route HDI PCB designs with a focus on stackup decisions, escape routing, and signal/power integrity.
Stackup Design and Microvia Strategy for HDI Routing
The first step in HDI routing is not drawing traces—it is defining the build-up. HDI boards use one or more sequential lamination cycles. A 1+N+1 stackup adds one microvia layer on each side of a conventional core, while a 2+N+2 stackup adds two, and 3+N+3 adds three. The higher the build-up count, the more routing freedom you gain, but the cost and fabrication complexity also increase. A fine-pitch BGA with 0.4 mm or 0.35 mm spacing often requires at least a 2+N+2 stackup, whereas a 0.8 mm pitch device can frequently be routed with a simpler 1+N+1 design. Selecting the right stackup early prevents the need to force routes through impossible via patterns later.
Within that stackup, the via strategy is central. Blind microvias connect an outer layer to one or two inner layers and are formed by laser drilling. They typically have a 0.1 mm to 0.15 mm diameter and require an aspect ratio of approximately 1:1 for reliable plating. Buried vias connect internal layers without reaching the surface, while via-in-pad places the via directly under a component pad. This is common in HDI design because it eliminates the dog-bone escape trace and saves significant space. However, via-in-pad requires copper filling and planarization to create a solderable surface; otherwise, solder can wick into the hole or leave a dimple that compromises assembly.
Microvias can be arranged as staggered or stacked. Staggered microvias shift their X/Y position on each sequential layer, which is less costly and easier to plate. Stacked microvias occupy the same drill position across multiple layers, providing the highest density and shortest vertical transitions for power and high-speed signals, but they require multiple fill and planarization steps. Your choice should be driven by the pin density, signal speed, and manufacturing budget. Many layout engineers use a hybrid approach: stacked vias for critical power and ground, staggered vias for general signal fanout.
Stackup symmetry and copper balance also affect routing success. HDI layers are thin, often 50 µm or less, which makes the board more sensitive to warpage during lamination. Keeping the build-up symmetric and distributing copper evenly across the panel helps maintain flatness for laser drilling and fine-line imaging. Before placing the first component, designers should align their layer stack with actual fabrication capabilities. A process-specific resource such as How To Route HDI PCB can clarify the practical limits of laser via depth, pad sizes, and sequential lamination sequences for a given design.
Escape Routing and Fanout for Fine-Pitch BGAs
Once the stackup is defined, the next major challenge is escape routing. Fine-pitch BGAs and QFN packages leave very little room between pads. For a 0.8 mm pitch BGA, a conventional dog-bone fanout with a small through via may still work if the routing density is moderate. At 0.65 mm pitch and below, through vias consume too much space and break the pad structure, so designers must switch to via-in-pad with microvias. A 0.5 mm pitch BGA with 0.25 mm pads leaves a gap of only 0.25 mm between pads. This is enough for a single 75 µm trace with 75 µm spacing, but not for both a via and a trace. Via-in-pad solves this by moving the transition under the component pad.
A reliable fanout sequence begins at the outer perimeter of the package. The outermost rows can often route directly on the surface layer without a via. The second or third row may use a microvia to drop to the next inner layer. Inner rows then escape on deeper layers using buried vias or additional microvia transitions. Establishing a clear layer transition map for each row is essential. Without it, inner rows block outer routes, and the design quickly becomes unroutable.
For a 0.4 mm pitch device, even via-in-pad with a single microvia may not be enough. The microvia capture pad must be small enough to fit inside the component pad, while still leaving enough annular ring for laser drill alignment. Typical HDI rules use a 0.1 mm microvia in a 0.25 mm pad, with the component pad diameter around 0.25 mm to 0.3 mm. The fabricator may use laser direct imaging and plugged via fill to achieve these geometries. If the pad is too small for a reliable via, you may need to reduce the number of signal pins per layer or add another buildup cycle.
Routing channels are also tied to stackup depth. A 2+N+2 stackup gives two outer microvia layers on each side, allowing row one to drop to layer 2 and row two to drop to layer 3 without interfering. The inner layers can then be used for long-distance routing and power distribution. Designers should route short escape segments first, then connect them to wider traces once the signal has escaped the BGA field. This keeps the dense area as clean as possible and prevents long parallel runs that increase crosstalk under the package.
Signal Integrity, Power Integrity, and DFM for HDI Routing
HDI routing is not just about fitting traces. The same high-density environment that saves space also increases the risk of signal integrity problems. Because HDI dielectrics are thinner, a 50 Ω single-ended trace can be much narrower than on a standard board. Differential pairs, such as 100 Ω USB or PCIe, also benefit from tight ground coupling. Keep high-speed signals on layers adjacent to a continuous ground plane, and avoid routing them over split planes or large voids. The return current path should be as short and direct as possible. Microvias are excellent for high-speed signals because their short barrel length introduces far less inductance and stub resonance than a through via. Whenever possible, transition high-speed signals through microvias rather than through holes.
Crosstalk becomes more severe as trace spacing shrinks. In fine-pitch areas, a 75 µm trace with 75 µm spacing may meet basic manufacturing rules but still create unacceptable coupling for sensitive clocks or serial links. Where space allows, increase the spacing to at least twice the dielectric thickness or use a guard trace with vias to shield the victim line. Differential pairs should be length matched within the package escape region, not just on the main routing path. Small mismatches under the BGA can accumulate and degrade signal quality.
Power integrity is another critical part of HDI layout. The thin dielectric between power and ground planes creates embedded planar capacitance, which helps reduce high-frequency noise. Designers should use dedicated power and ground plane pairs in the HDI stackup rather than routing power on signal layers. Decoupling capacitors should be placed directly under or around the BGA, using via-in-pad to minimize loop inductance. A poor decoupling network can cause voltage droop and electromagnetic interference even if the signal traces are clean.
Finally, design for manufacturability must guide every HDI routing decision. Microvia aspect ratios, copper fill type, annular ring size, and panel utilization all affect yield. Avoid non-functional pads on inner layers where they are not needed, as they add capacitance and complicate drilling. Use teardrops at the junction of trace and via to improve etch robustness. Specify filled and plated microvias for via-in-pad locations, and confirm that the fabrication partner can hold the required laser drill registration. Small routing choices—such as keeping a minimum microvia pitch, balancing copper on outer layers, and avoiding overly aggressive trace necking—can mean the difference between a stable high-volume HDI PCB and a board that suffers from opens, shorts, or assembly defects.
Edinburgh raised, Seoul residing, Callum once built fintech dashboards; now he deconstructs K-pop choreography, explains quantum computing, and rates third-wave coffee gear. He sketches Celtic knots on his tablet during subway rides and hosts a weekly pub quiz—remotely, of course.